In recent years, a semiconductor in which various circuits are integrated on the same insulating surface has been developed, and a phase-locked loop circuit (hereinafter, a PLL circuit) is known as a circuit of generating a clock with an arbitrary frequency synchronized with a supplied signal.
A PLL circuit includes a voltage controlled oscillator circuit (hereinafter, a VCO circuit) and compares a phase of a supplied signal with that of a feedback signal which is an output of the VCO circuit. Then, the PLL circuit adjusts an output signal by negative feedback so that the supplied signal and the feedback signal can maintain a fixed phase relationship between the signals.
In the VCO circuit, a frequency Fo of an output signal is controlled by an input voltage (hereinafter, also referred to as a control voltage of the VCO circuit) Vin (note that a voltage refers to a potential difference from a ground unless particularly described), and a relationship between the input voltage and the output frequency is changed by fluctuation of a power supply voltage. Therefore, by providing a constant voltage circuit in the VCO circuit, stable phase synchronization of the PLL circuit is achieved. However, a voltage to be generated by the constant voltage circuit fluctuates by fluctuation in a manufacturing condition such as a process. When the voltage to be generated by the constant voltage circuit fluctuates, the relationship between the input voltage Vin of the VCO circuit and the frequency Fo of the output signal fluctuates. Further, when the relationship between the input voltage Vin of the VCO circuit and the frequency Fo of the output signal fluctuates, the PLL circuit using the VCO circuit may not perform such an operation that a frequency of an output signal thereof (a free-running oscillation frequency) is made a desired frequency (hereinafter, also called locking with a desired frequency). Therefore, the range of the power supply voltage of the VCO circuit, which is capable of phase synchronization with the signal supplied to the PLL circuit, is required to be sufficiently enlarged.
As a measure against the foregoing problem, there is a method of enlarging the frequency range of an output signal of the VCO circuit. This can ensure that the PLL circuit locks with the desired frequency regardless of fluctuation of a power supply voltage due to various causes.
Variable range of the frequency Fo of the output signal with respect to the input voltage Vin of the VCO circuit is enlarged. Therefore, change rate (hereinafter, a frequency control voltage gain) of the frequency Fo of the output signal with respect to the input voltage Vin (hereinafter, also called a control voltage) becomes steep. As the frequency control voltage gain increases, the fluctuation of the frequency Fo of the output signal is increased even with respect to slight fluctuation of the control voltage, which gives an adverse effect on characteristics, such as a jitter (: fluctuation in delay time of a signal or the like).
In such a situation, for stable locking regardless of fluctuation of the operating condition and the manufacturing condition of a circuit, a PLL circuit is proposed in which a plurality of VCO circuits is provided, respective frequency ranges of output signals of the plurality of VCO circuits are set to different ranges, and the most suitable VCO circuit is selected from the plurality of VCO circuits (see Patent Document 1: Japanese Patent Laid-Open No. 2001-251186).
However, in the conventional PLL circuit, it is required to provide a plurality of VCO circuits, and to provide a selection circuit for selecting the most suitable VCO circuit. Therefore, there is a disadvantage in that circuit size is increased. In addition, since the frequency ranges of the output signals of the plurality of VCO circuits are discrete, locking of the PLL circuit may be unstable in the boundary of the frequency ranges.